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22 a, rrio, cmos,18 v operational ampli fier s data sheet AD8657 / ad8659 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no r esponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features micropower at high voltage (18 v): 22 a maximum low o ffset voltage: 350 v maximum low input bias current: 20 pa maximum gain bandwidth product: 23 0 khz at a v = 100 typical unity - gain crossover: 230 k hz ?3 db closed - loop bandwidth: 305 k hz sin gle - supply operation: 2.7 v to 18 v dual - supply operation: 1.35 v to 9 v unity - gain stable excellent electromagnetic interference immunity applications portable operating systems current monitors 4 ma to 20 ma loop drivers buffer/level shifting multipol e filters remote/wireless sensors low power transimpedance amplifiers general description the AD8657 / ad8659 are dual and quad micropower, precision, rail - to - rail inp ut/output amplifiers optimized for low power and wide operating supply voltage range applications. the AD8657 / ad8659 operate from 2.7 v to 18 v with a typical quiesce nt supply current of 18 a. the devices use the analog devices, inc., patented digitrim? trimming technique, which achieves low offset voltage. the AD8657 / ad8659 also have high immunit y to electromagnetic interference. the combination of low supply current, low offset voltage, very low input bias current, wide supply range, and rail - to - rail input and output make the AD8657 / ad8659 ideal for current monitoring in process and motor control applications. the combination of precision specifications makes these devices ideal for dc gai n and buffering of sensor front ends or high impedance input sources i n wireless or remote sensors or transmitters. the AD8657 / ad8659 are specified over the extended industrial temperat ure range (?40c to +125c). the AD8657 is available in an 8 - lead msop package and an 8 - lead lfcsp package; the ad8659 is available in a 14 - lead soic package and 16 - lead lfcsp package. pin connection diagr am s out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 AD8657 top view (not to scale) 08804-001 figure 1. AD8657 pin configuration, 8 - lead msop 08804-061 AD8657 top view ( not to scale) notes 1. connect the exposed p ad t o v? or le a ve it unconnected. 3 +in a 4v? 1 out a 2 ?in a 6 ?in b 5 +in b 8 v+ 7 out b figure 2. AD8657 pin configuration, 8 - lead lfcsp note: for ad8659 pin connections and for more information about the pin connections for these products, see the pin configurations and function descriptions section. 0 10 20 30 40 50 60 ?50 ?25 0 25 50 75 100 125 i sy per am p (a) tempera ture (c) v sy = 2.7v v sy = 18v 08804-023 figure 3. AD8657 , supply current vs. temperature table 1 . precision micropower op amps (<250 a) supply voltage 5 v 12 v to 16 v 36 v single ad8538 op196 ad8603 ada4051 -1 dual ad8539 AD8657 ad8622 ad8607 ada4091 -2 ada4051 -2 ada4096 -2 quad ad8609 ad8659 ad8624 ada4091 -4 ada4096 -4 free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 pin connection diagrams ............................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 18 v operation ............................. 3 electrical characteristics 10 v operation ............................. 4 electrical characteristics 2.7 v operation ............................ 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ..............................................9 applications information .............................................................. 19 input stage ................................................................................... 19 output stage ................................................................................ 20 rail to rail ................................................................................... 20 resistive load ............................................................................. 20 comparator operation AD8657 ........................................... 21 emi rejection ratio .................................................................. 22 4 ma to 20 ma process control current loop transmitter AD8657 ........................................................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 8 /1 2 rev. a to rev. b added ad8659 ................................................................... universal changes to features section ............................................................ 1 changes to pin connection diagrams section ............................ 1 added figure 3 , renumbered figures sequentially ..................... 1 changes to table 1 ............................................................................ 1 reordered table 2 and table 4 ........................................................ 3 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 4 changes to table 4 ............................................................................ 5 changes to table 6 ................................ ............................................ 6 added pin configurations and function descriptions section 7 added figure 4 and figure 5 ........................................................... 7 added table 7 , renumbered tables sequentially ........................ 7 added figure 6 and figure 7 ........................................................... 8 added table 8 .................................................................................... 8 changes to figure 10 and figure 13 ............................................... 9 changes to figure 14, figure 15, figure 17, and figure 18 ....... 10 changes to figure 28 and figure 31 ............................................. 12 changes to figure 32 ...................................................................... 13 changes to figure 39 ...................................................................... 14 changes to figure 63 and figure 66 ............................................. 18 moved figure 68 ............................................................................. 19 change to inverting op amp configu ration section heading and changes to figure 70 .............................................................. 20 ch ange to noninverting op amp configuration heading and changes to figure 71 ...................................................................... 20 change to comparator operation AD8657 heading ............ 21 change to 4 ma to 20 ma process control current loop transmitter AD8657 sect ion heading and changed 33 a to 34 a ................................................................................ 22 updated outline dimensions ....................................................... 24 added figure 81 and figure 82 .................................................... 24 changes to ordering guide .......................................................... 24 3/11 rev. 0 to rev. a added lfcsp package information ........................... throughout added figure 2, renumbered subsequent figures .................... 1 changes to table 2, introductory te xt; input characteristics, offset voltage and common - mode rejection ratio test conditions/comments; and dynamic performance, phase marg in value s .................................................................................... 3 changes to table 3, introductory text; input characteristics, offset voltage and common - mode rejection ra tio test conditions/comments ..................................................................... 4 changes to table 4, introductory text; input characteristics, offset voltage and common - mode rejection ratio test conditions/comments ..................................................................... 5 changes to thermal resistance section and table 5 ................... 6 updated outline dimensions ....................................................... 21 chan ges to ordering guide .......................................................... 21 1 /11 revision 0: initial version free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 3 of 24 specifications electrical character istics 18 v operation v sy = 18 v, v cm = v sy / 2 v, t a = 25c, unless otherwise specified. table 2 . parameter symbol test conditions/comm ents min typ max unit input characteristics offset voltage v os v cm = 0 v to 18 v 350 v v cm = 0.3 v to 17.7 v , ?40c t a +85c 1.8 mv v cm = 0.3 v to 17.7 v , ?40c t a +125c 2 mv v cm = 0 v to 18 v , ?40c t a +125c 16 mv input bias current i b 5 20 pa ?40c t a +125c 2.9 na input offset current i os 40 pa ?40c t a +125c 5.8 na input voltage range 0 18 v common - mode rejection ratio cmrr v cm = 0 v to 18 v 94 110 db v cm = 0.3 v to 17.7 v , ?40c t a +85c 82 db v cm = 0.3 v to 17.7 v , ?40c t a +125c 80 db v cm = 0 v to 18 v , ?40c t a +125c 64 db large signal voltage gain a vo r l = 100 k?, v o = 0.5 v to 17.5 v 115 120 db ?40c t a +125c 105 db offset voltage drift v os /t 2 v/c input resistance r in 10 g? input capacitance, differential mode c indm 11 pf input capacitance, common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k? to v cm , ?40c t a +125c 17.97 v output voltage low v ol r l = 100 k? to v cm , ?40c t a +125c 30 mv short - circuit current i sc 12 ma closed - loop output impedance z out f = 1 khz, a v = 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 100 115 db ?40c t a +125c 90 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 34 a dyna mic performance slew rate sr r l = 1 m?, c l = 10 pf, a v = 1 80 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k?, c l = 10 pf 15 s unity - gain crossover ugc v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 1 230 khz phase margin m v in = 10 mv p-p, r l = 1 m?, c l = 10 pf, a v = 1 60 degrees gain bandwidth product gbp v in = 10 mv p-p, r l = 1 m?, c l = 10 pf, a v = 100 230 khz ?3 db closed - loop bandwidth f ? 3 db v in = 10 mv p-p, r l = 1 m?, c l = 10 pf, a v = 1 305 khz channel separation cs f = 10 khz, r l = 1 m? 95 db emi rejection ratio of +in x emirr v in = 100 mv peak ; f = 400 mhz, 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 5 v p -p voltage noise density e n f = 1 khz 50 n v/hz f = 10 khz 45 nv/hz current noise density i n f = 1 khz 0.1 pa/hz free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 4 of 24 electrical character istics 10 v operation v sy = 10 v, v cm = v sy /2 v , t a = 25c, unless otherwise specified. table 3 . parameter symbol test condi tions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 10 v 350 v v cm = 0.3 v to 9.7 v , ?40c t a +85c 1.6 mv v cm = 0.3 v to 9.7 v , ?40c t a +125c 2 mv v cm = 0 v to 10 v , ?40c t a +125c 16 mv input bias current i b 2 15 pa ?40c t a +125c 2.6 na input offset current i os 30 pa ?40c t a +125c 5.2 na input voltage range 0 10 v common - mode rejection ratio cmrr v cm = 0 v to 10 v 88 105 db v cm = 0.3 v to 9.7 v , ?40c t a +85c 76 db v cm = 0.3 v to 9.7 v , ?40c t a +125c 75 db v cm = 0 v to 10 v, ?40c t a +125c 59 db large signal voltage gain a vo r l = 100 k?, v o = 0.5 v to 9.5 v 108 120 db ?40c t a +125c 100 db offset voltage drift v os /t 2 v/c input resistance r in 10 g? input capacitance, differential mode c indm 11 pf input capacitance, common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k? to v cm , ?40c t a +125c 9.98 v output voltage low v ol r l = 100 k? to v cm , ?40c t a +125c 20 mv short - circuit current i sc 11 ma closed - loop output impedance z out f = 1 khz, a v = 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 10 0 11 5 db ?40c t a +125c 90 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 34 a dynamic performance slew rate sr r l = 1 m?, c l = 10 pf, a v = 1 75 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k? , c l = 10 pf 15 s unity - gain crossover ugc v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 1 225 khz phase margin m v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 1 60 degrees gain bandwidth product gbp v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 10 0 230 khz ? 3 db closed - loop bandwidth f ? 3 db v in = 10 mv p - p, r l = 1 m?, c l = 10 pf, a v = 1 300 khz channel separation cs f = 10 khz, r l = 1 m? 95 db emi rejection ratio of +in x emirr v in = 100 mv peak ; f = 400 mhz, 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 5 v p -p voltage noise density e n f = 1 khz 50 nv/hz f = 10 khz 45 nv/hz current noise density i n f = 1 khz 0.1 pa/hz free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 5 of 24 electrical character istics 2.7 v operation v sy = 2.7 v, v cm = v sy / 2 v, t a = 25c, unless otherwise specified. table 4 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 2.7 v 350 v v cm = 0.3 v to 2 .4 v , ?40c t a +85c 1.2 mv v cm = 0.3 v to 2.4 v , ?40c t a +125c 2.5 mv v cm = 0 v to 2.7 v , ?40c t a +125c 16 mv input bias current i b 1 10 pa ?40c t a +125c 2.6 na input offset current i os 20 pa ?40c t a +125c 5.2 na input voltage range 0 2.7 v common - mode rejection ratio cmrr v cm = 0 v to 2.7 v 77 95 db v cm = 0.3 v to 2.4 v , ?40c t a +85c 69 db v cm = 0.3 v to 2.4 v , ?40c t a +125c 62 db v cm = 0 v to 2.7 v , ?40c t a +125c 47 db large signal voltage gain a vo r l = 100 k?, v o = 0.5 v to 2.2 v 95 105 db ?40c t a +125c 90 db offset voltage drift v os /t 2 v/c input resistance r in 10 g? input capacitance, differential mode c indm 11 pf input capacitance, common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k? to v cm , ?40c t a +125c 2.69 v output voltage low v ol r l = 100 k? to v cm , ?40c t a +125c 10 mv short - circuit current i sc 4 ma closed - loop out put impedance z out f = 1 khz, a v = 1 20 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 100 115 db ?40c t a +125c 90 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 34 a dynamic performance slew rate sr r l = 1 m?, c l = 10 pf, a v = 1 50 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k?, c l = 10 pf 20 s unity - gain crossover ugc v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 1 190 khz phase margin m v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 1 55 degrees gain bandwidth product gbp v in = 10 mv p- p, r l = 1 m?, c l = 10 pf, a v = 100 200 khz ? 3 db closed - loop bandwidth f ? 3 db v in = 10 mv p - p, r l = 1 m?, c l = 10 pf, a v = 1 245 khz channel separation cs f = 10 khz, r l = 1 m? 95 db emi rejection ratio of +in x emirr v in = 100 mv peak ; f = 400 mhz, 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 6 v p -p voltage noise density e n f = 1 khz 60 nv/ hz f = 10 khz 56 nv/hz current noise density i n f = 1 khz 0.1 pa/hz free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 6 of 24 absolute maximum rat ings table 5. parameter rating supply voltage 20.5 v input voltage (v?) ? 300 mv to (v+) + 300 mv input current 1 10 ma di fferential input voltage v sy output short - circuit duration to gnd indefinite temperature range s storage ? 65 c to +150c operating ? 40c to +125c junction ? 65c to +150c lead temperature (soldering, 60 sec) 300c 1 the input pins have clamp d iodes to the power supply pins. limit t he input current to 10 ma or less whenever input signals exceed the power supply rail by 0.3 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rat ing only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. thermal resistance ja is specified for the worst - case conditio ns, that is, a device soldered i n a circuit board for surface - mount packages using a standard 4 - layer j edec board. the exposed pad ( lfcsp package s only) is soldered to the board. table 6 . thermal resistance package type ja jc unit 8 - lead msop (rm - 8) 142 45 c/w 8- lead lfcsp (cp -8- 11) 75 12 c/w 14- lead soic (r - 14) 115 36 c/w 16- lead lfcsp (cp -16-20 ) 52 13 c/w esd caution free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 7 of 24 pin configurations a nd f unction descriptions out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 AD8657 top view (not to scale) 08804-001 figure 4. AD8657 pin configuration, 8 - lead msop 08804-061 AD8657 top view (not to scale) notes 1. connect the exposed p ad t o v? or le a ve it unconnected. 3 +in a 4v? 1 out a 2 ?in a 6 ?in b 5 +in b 8 v+ 7 out b figure 5. AD8657 pin configuration, 8- lead lfcsp table 7 . pin function descriptions , AD8657 pin no. 1 mnemonic description 8- lead msop 8- lead lfcsp 1 1 out a output channel a. 2 2 ?in a negative input channel a. 3 3 +in a positive input channel a. 4 4 v? negative supply voltage. 5 5 +in b positive input channel b. 6 6 ?in b negative input channel b. 7 7 out b output channel b. 8 8 v+ positive supply voltage. n/a ep 2 e pad exp osed pad. for the AD8657 (8 - lead lfcsp only), connect the exposed pad to v? or leave it unconnected. 1 n/a means not applicable. 2 the exposed pad is not shown in the pin configuration diagram. free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 8 of 24 out a 1 ?in a 2 +in a 3 v+ 4 out d 14 ?in d 13 +in d 12 v? 11 +in b 5 +in c 10 ?in b 6 ?in c 9 out b 7 out c 8 ad8659 top view (not to scale) 08804-103 figure 6. ad8659 pin configur ation, 14 - lead soic_n notes 1. nic = no internal connection. 2. connect the exposed p ad t o v ? or le a ve it unconnected. 12 11 10 1 3 4 ?in d +in d v? 9 +in c ?in a v+ 2 +in a +in b 6 out b 5 ?in b 7 out c 8 ?in c 16 nic 15 out a 14 out d 13 nc top view (not to scale) ad8659 08804-104 figure 7. ad8659 pin configuration , 16 - lead lfcsp table 8 . pin function descriptions, ad8659 pin no. 1 mnemonic description 14- lead soic 16- lead lfcsp 1 15 out a output channel a. 2 1 ?in a negative input channel a. 3 2 +in a positive input channel a. 11 10 v? negative supply voltage. 5 4 +in b positive input channel b. 6 5 ?in b negative input channel b. 7 6 out b output channel b. 4 3 v+ positive supply voltage. 8 7 out c outp ut channel c. 9 8 ?in c negative input channel c. 10 9 +in c positive input channel c. 12 11 +in d positive input channel d. 13 12 ?in d negative input channel d. 14 14 out d output channel d. n/a 13 nic no internal connection . n/a 16 nic no i nterna l connection . n/a ep 2 e pad 2 exposed pad. for the ad8659 (16 - lead lfcsp only), connect the exposed pad to v? or leave it unconnected. 1 n/a means not appl icable. 2 the exposed pad is not shown in the pin configuration diagram. free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 9 of 24 typical performance characteristics t a = 25 c, unless otherwise noted. 20 40 60 80 100 120 140 160 number of amplifiers v sy = 2.7v v cm = v sy /2 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 v os (v) 08804-002 figure 8 . input offset voltage distribution 0 2 4 6 8 10 12 14 16 18 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 number of amplifiers tcv os (v/c) v sy = 2.7v C40c t a +125c 08804-003 figure 9 . input offset voltage drift distribution ?350 ?250 ?150 ?50 50 150 250 350 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (v) v cm (v) v sy = 2.7v 08804-207 figure 10 . input offset voltage vs. common - mode voltage 0 20 40 60 80 100 120 140 160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 number of amplifiers v os (v) v sy = 18v v cm = v sy /2 08804-005 figure 11 . input offset voltage distribution 0 2 4 6 8 10 12 14 18 16 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 number of amplifiers tcv os (v/c) v sy = 18v C40c t a +125c 08804-006 figure 12 . input offset voltage drift distribution ?350 ?250 ?150 ?50 50 150 250 350 0 2 4 6 8 10 12 14 16 18 v os (v) v cm (v) 08804-210 v sy = 18v figure 13 . input offset voltage vs. common - mode voltage free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 10 of 24 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) v sy = 2.7v ?40 c t a + 85 c 08804-2 11 figure 14 . input offset voltage vs. common - mode voltage ?6 ?4 ?2 0 2 4 6 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) v sy = 2.7v C40c t a +125c 08804-212 figure 15 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) tempera ture (c) i b + i b ? v sy = 2.7v 08804-008 figure 16 . input bias current vs. temperature ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12 14 16 18 v os (mv) v cm (v) v sy = 18v ?40 c < t a < + 85c 08804-214 figu re 17 . input offset voltage vs. common - mode voltage ?6 ?4 ?2 0 2 4 6 0 2 4 6 8 10 12 14 16 18 v os (mv) v cm (v) v sy = 18v C40c t a +125c 08804-215 figure 18 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) tempera ture (c) v sy = 18v 08804-0 11 i b + i b ? figure 19 . input bias current vs. temperature free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 11 of 24 ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i b (na) v cm (v) 25c 85c 125c v sy = 2.7v 08804-009 figure 20 . input bias current vs. common - mode voltage 0.01m 0.1m 1m 10m 100m 1 10 0.001 0. 01 0.1 1 10 100 output vo lt age (v oh ) t o supp ly rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 08804-010 figure 21 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0. 01 0.1 1 10 100 output vo lt age (v ol ) t o supp ly rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 08804-014 figure 22 . output voltage (v ol ) to supply rail vs. load current 0 2 4 6 8 10 12 14 16 18 v cm (v) 25c 85c 125c v sy = 18v 08804-012 ?4 ?3 ?2 ?1 0 1 2 3 4 i b (na) figure 23 . input bias current vs. common - mode voltage 0.01m 0.1m 1m 10m 100m 1 10 output vo lt age (v oh ) t o supp ly rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 0.001 0.01 0.1 1 10 100 08804-013 figure 24 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0. 01 0.1 1 10 100 output vo lt age (v ol ) t o supp ly rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 08804-017 figure 25 . output voltage (v ol ) to supply rail vs. load current free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 12 of 24 2.695 2.696 2.697 2.698 2.699 2.700 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) tempera ture (c) r l = 100k? r l = 1m? v sy = 2.7v 08804-015 figure 26 . output voltage (v oh ) vs. temperature 0 2 4 6 8 10 12 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) tempera ture (c) r l = 100k? r l = 1m? v sy = 2.7v 08804-016 figure 27 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i sy per am p (a) v cm (v) ?40c +25c +85c +125c v sy = 2.7v 08804-225 figure 28 . supply current vs. common - mode voltage 17.975 17.980 17.985 17.990 17.995 18.000 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) tempera ture (c) r l = 100k? r l = 1m? v sy = 18v 08804-018 figure 29 . output voltage (v oh ) vs. temperature 0 2 4 6 8 10 12 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) tempera ture (c) r l = 100k? r l = 1m? v sy = 18v 08804-019 figure 30 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 3 6 9 12 15 18 i sy per am p (a) v cm (v) v sy = 18v ?40c +25c +85c +125c 08804-228 figure 31 . supply current vs. common - mode voltage free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 13 of 24 0 5 10 15 20 25 30 35 40 0 3 6 9 12 15 18 ?40c +25c +85c +125c i sy per am p (a) v sy (v) 08804-229 figure 32 . supply current vs. supply voltage ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 1k 10k 100k 1m phase (degrees) open-loop gain (db) frequenc y (hz) v sy = 2.7v r l = 1m? phase gain 08804-021 c l = 10pf c l = 100pf figure 33 . open - loop gain and phase vs. frequency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 2.7v a v = 100 a v = 10 a v = 1 08804-022 figure 34 . closed - loop gain vs. frequency 0 10 20 30 40 50 60 ?50 ?25 0 25 50 75 100 125 i sy per am p (a) tempera ture (c) v sy = 2.7v v sy = 18v 08804-023 figure 35 . supply current vs. temperature 1k 10k 100k 1m open-loop gain (db) frequenc y (hz) v sy = 18v r l = 1m? 08804-024 phase c l = 10pf c l = 100pf ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 gain phase (degrees) figure 36 . open - loop gain and phase vs. frequency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 18v a v = 100 a v = 10 a v = 1 08804-025 figure 37 . closed - loop gain vs. frequency free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 14 of 24 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 2.7v a v = 1 a v = 10 a v = 100 08804-026 figure 38 . output impedance vs. frequency 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) 08804-236 v sy = 2.7v v cm = v sy /2 figure 39 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 2.7v 08804-028 figure 40 . psrr vs. frequency 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 18v a v = 1 a v = 10 a v = 100 08804-029 figure 41 . output impedance vs. frequency 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v sy = 18v v cm = v sy /2 0 20 40 60 80 100 120 140 08804-030 figure 42 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 18v 08804-031 figure 43 . psrr vs. frequency free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 15 of 24 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) v sy = 2.7v v in = 10mv p-p r l = 1m? os+ os? 08804-032 figure 44 . small signal overshoot vs. load capacitance time (100s/div) voltage (500mv/div) v sy = 1.35v a v = 1 r l = 1m? c l = 100pf 08804-033 figure 45 . large signal transient response time (100s/div) voltage (5mv/div) v sy = 1.35v a v = 1 r l = 1m? c l = 100pf 08804-034 figure 46 . small signal tr ansient response 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) v sy = 18v v in = 10mv p-p r l = 1m? os+ os? 08804-035 figure 47 . small signal overshoot vs. load capacitance time (100s/div) voltage (5v/div) v sy = 9v a v = 1 r l = 1m? c l = 100pf 08804-036 figure 48 . large signal transient response time (100s/div) voltage (5mv/div) v sy = 9v a v = 1 r l = 1m? c l = 100pf 08804-037 figure 49 . small signal transient response free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 16 of 24 time (40s/div) ?0.4 ?0.2 0 2 1 0 input voltage (v) output voltage (v) v sy = 1.35 a v = ?10 r l = 1m? input output 08804-039 figu re 50 . positive overload recovery time (40s/div) 0 0.2 0.4 0 ?1 ?2 input voltage (v) output voltage (v) v sy = 1.35v a v = ?10 r l = 1m? input output 08804-038 figure 51 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k? c l = 10pf input output error band 08804-040 figure 52 . positive settling time to 0.1% time (40s/div) ?1 0 ?2 10 5 0 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m? input output 08804-042 figure 53 . positive overload recovery time (40s/div) 0 1 2 0 ?5 ?10 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m? input output 08804-041 figure 54 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 18v r l = 100k? c l = 10pf input output error band 08804-043 figure 55 . positive settling time to 0.1% free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 17 of 24 time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k? c l = 10pf input output error band 08804-044 figure 56 . negative settling time to 0.1% 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/hz) frequenc y (hz) v sy = 2.7v 08804-045 figure 57 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 2.7v 08804-046 figure 58 . 0.1 hz to 10 hz noise time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy =18v r l = 100k? c l = 10pf input output error band 08804-047 figure 59 . negative settling time to 0.1% 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/hz) frequenc y (hz) v sy = 18v 08804-048 figure 60 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 18v 08804-049 figure 61 . 0.1 hz to 10 hz noise free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 18 of 24 0 0.5 1.0 1.5 2.0 2.5 3.0 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) v sy = 2.7v v in = 2.6v r l = 1m? a v = 1 08804-050 figure 62 . output swing vs. frequency 0.01 0.1 1 10 10 100 1k 10k 100k thd + n (%) frequenc y (hz) v sy = 2.7v v in = 0.2v rms r l = 1 m? a v = 1 08804-260 figure 63 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v in = 0.5v p-p v in = 1.5v p-p v in = 2.6v p-p v sy = 2.7v r l = 1m? a v = ?100 08804-052 r l 1m? 10k? figure 64 . channel separation vs. f requency 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) 0 2 4 6 8 10 12 14 16 18 20 v sy = 18v v in = 17.9v r l = 1m? a v = 1 08804-053 figure 65 . output swing vs. frequency 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) 08804-263 v sy = 18v v in = 0.2v rms r l = 1 m? a v = 1 figure 66 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v sy = 18v r l = 1m? a v = ?100 v in = 1v p-p v in = 5v p-p v in = 10v p-p v in = 15v p-p v in = 17v p-p 08804-055 r l 1m? 10k? figure 67 . channel separation vs. frequency free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 19 of 24 applications informa tion v+ v? +in x r1 d1 d2 m1 m2 m7 m6 m3 m4 m5 vb1 m8 m10 m9 m16 m17 m11 vb2 out x m12 m14 m13 m15 i1 r2 ?i n x 08804-056 figure 68 . simplified schematic the AD8657 / ad8659 are low power, rail - to - rail input and output precision cmos amplifier s that operate over a wide sup ply voltage range of 2.7 v to 18 v. t h e AD8657 / ad8659 use the analog devices digitrim technique to achieve a higher degree of precision than is available from other cmos amplifiers . the digitrim techniqu e is a method of trimming the offset volta ge of an amplifier after assembly. the advantage of post - package trim ming is that it corrects any shifts in offset voltage caused by mechanical stresses of assembly. the AD8657 / ad8659 also employ unique input and output stages to achieve a rail - to - rail input and output range with a very low supply current. input stage figure 68 shows the simplified schematic of the AD8657 / ad8659 . the input st age comprises two differential transistor pairs, an nmos pair (m1, m2) and a pmos pair (m3, m4). the input common - mode voltage determines which differential pair turns on and is more active than the other . the pmos differential pair is active when the input voltage approaches and reaches the lower supply rail. the nmos pair is needed for input voltages up to and including the upper supply rail. this topology allows the amplifier to maintain a wide dynamic input voltage range and to maximize signal swing to both supply rails. for the majority of the input common - mode voltage range, the pmos differ ential pair is active. differen tial pairs commonly exhibit different offset voltages. the handoff from one pair to the other creates a step - like characteristic that is visible in the v os vs. v cm graph s ( see figure 10 an d figure 13 ). this characteristic is inherent in all rail -to- rail amplifiers that use the dual differential pair topology. therefore, always choose a common - mode voltage that does not include the region of handoff from one input d ifferential pair to the other. additional steps in the v os vs. v cm curves are also visible as the input common - mode voltage approaches the power supply rails. these changes are a result of the load transistors (m8, m9, m 14, and m15) running o ut of headroo m. as the load transistors are forced into the triode region of operation, the mismatch of their drain impedances contributes to the offset voltage of the amplifier. this problem is exacerbated at high temperatures due to the decrease in the threshold volt age of the input transistors (see figure 14 , figure 15 , figure 17 , and figure 18 for typ ical perfor - mance data ). current source i1 drives the pmos transistor pair. as the input common - mode voltage approaches the upper rail, i1 is steered away from the pmos differential pair through the m5 transistor . the bias voltage, vb1 (see figure 68 ), controls the point where this transfer occurs. m5 diverts the tail current into a current mirror consisting of the m6 and m7 transistors. the output of the current mirror then drives the nmos pair. note that the activation of this c urrent mirror causes a slight increase in supply current at high common - mode vo ltages ( see figure 28 and figure 31 for more details ). the AD8657 / ad8659 achieve their high performance by using low voltage mos devices for their differential inputs. these low voltage mos devices offer excellent noise and bandwidth per unit of current. ea ch differential input pair is protected by proprie - tary regulation circuitry (not shown in the simplified schematic). the regulation circuitry consists of a combination of active devices that maintain the pro per voltages across the input pairs during norma l operation and passive clamping devices that protect the amp lifier during fast transients. however, t hese passive clamping devices begin to forward bias as the common - mode voltage approaches either power supply rail , thereby causing an increase in the inp ut bias current (see figure 20 and figure 23 ). t he input devices are also protected from large differential input voltages by clamp diodes (d1 and d2). these diodes are buf fered from the inputs with two 10 k? resistors (r1 and r2). the differential diodes turn on whenever the differential voltage exceeds approx imately 600 mv; in this condition, the differential input resistance drops to 20 k?. free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 20 of 24 output stage the AD8657 / ad8659 feature a complementary output stage consisting of the m16 and m17 transistors. these transistors are configured in class ab topology and are biased by the voltage source, vb2. this topology allows the output voltage to go within millivolts of the supply rails, achieving a rail - to - rail output swing. the output voltage is limited by the output impedance of the transistors, which are low r on mos devices. the output vol tage swing is a function of the load current and can be estimated using the output voltage t o the supply rail vs. load current diagrams (see figure 21, figure 22, figure 24, and figure 25). rail to r ail the AD8657 / ad8659 feature rail - to - rail input and output with a supply voltage from 2.7 v to 18 v. figure 69 shows the input and output waveforms of the AD8657 / ad8659 configured as a unity - gain buffer with a supply voltage of 9 v and a resistive load of 1 m ? . with an input voltage of 9 v, the AD8657 / ad8659 allow the output to swing very close to both rails. additionally, they do not exhibit phase reversal. time (200s/div) voltage (5v/div) v sy = 9v r l = 1m? 08804-057 input output figure 69 . rail -to- rail input and output resistive l oad the f eedback resistor alters the load resistance that an amplifier sees. it is, therefore, important to be aware of the value of feed - back resistors chosen for use with the AD8657 / ad8659 . the amplifiers are capable of driving resistive loads down to 100 k? . the following two examples, inverting and noninverting configurations , show how the feedback resistor changes the actual load resistance seen at the output of the amplifier. inverting op amp configuration figure 70 shows the AD8657 / ad8659 in an inverting configu - ration with a resistive load, r l , at the output. the actual load seen by the amplifier is the parallel combination of the feed back resistor, r2 , and load , r l . for example, the combination of a feed - back resistor of 1 k? and a load of 1 m? results in an equivalent load resistance of 999 ? at the output. because the AD8657 / ad8659 are incapable of driving such a heavy load , perfor mance degrades greatly. to avoid loading the output, use a larger feedback resistor , but consider the resistor thermal noise effect on the overall circuit. AD8657/ ad8659 r1 r2 r l ?v sy r l, eff = r l || r2 +v sy v in v out 08804-058 figure 70 . inverting op amp configuration noninverting op amp configuration figure 71 shows the AD8657 / ad8659 in a noninverting configu - ratio n with a resistive load, r l , at the output. the actual load seen by the amplifier is the parallel combination of r1 + r2 and r l . r1 r2 r l ?v sy r l, eff = r l || (r1 + r2) +v sy v in v out 08804-059 AD8657/ ad8659 figure 71 . noninverting op amp configuration free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 21 of 24 comparator operation AD8657 an op amp is designed to operate in a closed -l oop configuration with feedback from its output to its inverting input. figure 72 shows the AD8657 c onfigured as a voltage follower with an input voltage that is always kept at midpoin t of the power supplies. the same configuration is applied to the unused channel . a1 an d a2 indicate the placement of ammeters to measure supply current. i sy + refers to the current flowing from the upper supply rail to the op amp, and i sy ? refers to the cu rrent flowing from the op amp t o the lower supply rail. as shown in figure 73 , as expected in normal operating condition, the total current flowing into the op amp is equivalent to the total current flowing out of the op amp, where, i sy + = i sy ? = 36 a for the dual AD8657 at v sy = 18 v. AD8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-066 figure 72 . voltage follower 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 i sy per dua l amplifier (a) v sy (v) i sy ? i sy + 08804-067 figure 73 . supply current vs. supply voltage (voltage follower) in contrast to op amps, comparato rs are designed to work in an open - loop configuration and to drive logic circuits. although op a mps are different from comparators, occasionally an unused section of a dual op amp is used as a comparator to save board space and cost ; h oweve r, this is not recommended. figure 74 and figure 75 show the AD8657 configured as a com - parator, with 100 k? resistors in series with the input pin s. any unused channels are configured as buffers with the input voltage kept at the midpoint of the power supplies. the AD8657 / ad8659 have input devices that are protected from large differential input voltages by diode d1 and diode d2 (r efer to figure 68 ) . these diodes consist of substrate pnp bipolar transistors, and conduc t whenever the differenti al input voltage exceeds approxi - mately 600 mv ; how ever, t hese diodes also allow a current path from the input to the lower supply rail, thus resulting in an increase in the total supply current of the system. as shown in figure 76 , both configurations yield the same result. at 18 v of power supply, i sy + remains at 36 a per dual amplifier, but i sy ? increases to 140 a in magni tude per dual amplifier. AD8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-068 figure 74 . c omparator a AD8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-069 figure 75 . comparator b 0 20 40 60 80 100 120 140 160 0 2 4 6 8 10 12 14 16 18 i sy per dua l amplifier (a) v sy (v) i sy ? i sy + 08804-070 figure 76 . supply current vs. supply voltage ( AD8657 as a comparator) n ote that 100 k ? resistors are used in series with the input of the op amp. if smaller resistor values are used, the supply current of the system increase s much more. for more details on op amps as comparators, refer to the an - 849 application note using op amps a s comparators . free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 22 of 24 emi rejection r atio circuit performance is often adversely affected by high frequency electromagnetic interference (emi). in the event where signal strength is low and transmission lines are long, an op amp must accurately amplify the input signals. however, all op amp pins th e non inverting input, inverting input, positive supply, negative supply , and output pins are susceptible to emi signals. these high frequency signals are coupled into an op amp by various means such as conduction, near field radiation, or far field radi - ation. for example , wires and pcb traces can act as antennas and pick up high frequency emi signals. precision op amps, such as the AD8657 and ad8659 , do not amplify emi or r f signals because of their relatively low ban dwidth. however, due to t he non linearities of the input devices, op amps can rectify these out - of - band signals. when these high frequency signals are rectified, they appear as a dc offset at the output. to d e s cr ibe the ability of the AD8657 / ad8659 to perform as intended in the presence of an electromagnetic energy, the e lectromagnetic i nterference r ejection ratio (emirr) of the non inverting pin is specified in table 2 , table 3 , and table 4 of the specifications section . a mathematical method of mea suring emirr is define d as follows: emirr = 20 log ( v in_peak / v os ) 20 40 60 80 100 120 140 10m 100m 1g 10g emirr (db) frequenc y (hz) v in = 100mv peak v sy = 2.7v t o 18v 08804-071 figure 77 . emirr vs. frequency 4 m a to 20 m a process control cu rrent loop transmitter AD8657 the 2 - wire current transmitters are often used in distributed control systems and process control applications to transmit analog signals between sensors and process controllers. figure 78 shows a 4 ma to 20 ma current loop transmitter. the transmitter powers directly from the control loop powe r supply , and the current in the loop carries signal from 4 ma to 20 ma. thus, 4 ma establishes the baseline current budget within which the circuit must operate. using the AD8657 is an excellent choice due to its low supply current of 34 a per amplifier over tempera ture and supply voltage. the current transmitter controls the current flowing in the loop, where a zero - scale input signal is represented by 4 ma of current and a full - scale input signal is represen ted by 20 ma. the transmitter also floats from the control loop power supply, v dd , while signal ground is in the receiver. the loop current is measured at the load resistor, r l , at the receiver side. at a zero - scale input, a current of v ref /r null flows th rough r ?. this creates a current flowing through the sense resistor, i sense , determined by the following equation (see figure 78 for details) : i sense, min = ( v ref r? )/( r null r sense ) with a full - scale input voltage, c urrent flowing through r ? is increased by the full - scale change in v in /r span . this creates an increase in the current flowing through the sense resistor. i sense, delta = ( full - scale change in v in r? )/( r span r sense ) therefore i sense, max = i sense, min + i sense, delta when r ? >> r sense , the current through the load resistor at the receiver side is almost equivalent to i sense . figure 78 is designed for a full - scale input voltage of 5 v. at 0 v of input, loop current is 3.5 ma ; an d at a full scale of 5 v, the loop current is 21 ma. this allows software calibration to fine tune the current loop to the 4 ma to 20 ma range. the AD8657 and adr125 both consume only 16 0 a quiescent current, making 3.34 ma current available to power additional signal conditioning circuitry or to power a bridge circuit. r l 100? v dd 18v c2 10f c3 0.1f c1 390pf c4 0.1f r4 3.3k? q1 d1 4ma to 20ma r3 1.2k? r null 1m? 1% v ref r span 200k? 1% v in 0v to 5v r1 68k? 1% r2 2k? 1% notes 1. r1 + r2 = r. 1/2 AD8657 c5 10f r sense 100? 1% 08804-060 v out gnd adr125 v in figure 78 . 4 ma to 20 ma current loop transmitter free datasheet http:///
data sheet AD8657/ad8659 rev. b | page 23 of 24 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 79 . 8 - lead mini small outline package [msop] (rm -8) dimensions shown in millimeters 2.44 2.34 2.24 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a sea ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic at or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 01-24-20 1 1-b figure 80 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very t hin, dual lead (cp -8- 11) dimensions shown in millimeters free datasheet http:///
AD8657/ad8659 data shee t rev. b | page 24 of 24 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equi v alents for reference on ly and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 81 . 14 - lead standard small outline package [soic_n] narrow body (r- 14) dimensions shown in millimeters and (inches) compliant to jedec standards mo-220-wggc-3. 1 0.65 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic at or 4.10 4.00 sq 3.90 0.50 0.40 0.30 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic at or 0.35 0.30 0.25 2.40 2.35 sq 2.30 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-18-2012-b figure 82 . 16 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 16 -20) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding AD8657armz ?40c to +125c 8- lead mini small outlin e package [msop] rm - 8 a2n AD8657armz -r7 ?40c to +125c 8- lead mini small outline package [msop] rm - 8 a2n AD8657armz -rl ?40c to +125c 8- lead mini small outline package [msop] rm - 8 a2n AD8657acpz -r7 ?40c to +125c 8- lead lead frame chip scale pack age [lfcsp_wd] cp -8- 11 a2n AD8657acpz -rl ?40c to +125c 8- lead lead frame chip scale package [lfcsp_wd] cp -8- 11 a2n ad8659arz ?40c to +125c 14- lead standard small outline package [soic_n] r- 14 ad8659arz - r7 ?40c to +125c 14- lead standard small o utline package [soic_n] r- 14 ad8659arz - rl ?40c to +125c 14- lead standard small outline package [soic_n] r- 14 ad8659acpz - r7 ?40c to +125c 16 - lead lead frame chip scale package [lfcsp_wq] cp - 16 - 2 0 ad8659acpz -rl ?40c to +125c 16- lead lead frame chip scale package [lfcsp_wq] cp -16 -20 1 z = rohs compliant part. ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08804 -0- 8/12(b) free datasheet http:///

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